x86 expert Christian Ludloff detailed new prefixes for the WBINVD instruction, used for Write Back and Invalidate Cache, on the Linux kernel mailing list. The disclosure comes from a “corporate entity other than Intel or AMD” and details skip hints for various cache levels. The identity of the entity remains unknown, though speculation links it to RosaicLabs.
The new skip hints allow the WBINVD instruction to bypass specific cache levels during write-back and invalidation processes. Specifically, the hints enable skipping L0i/L1i cache, L0d/L1d cache, invalidations, and the LLC (Last Level Cache). Additionally, six implementation-specific hints are defined, offering up to 64 potential behaviors depending on the processor.
The disclosed prefixes are as follows: 0x67 to skip L0i/L1i cache, 0x66 to skip L0d/L1d cache, 0xF3 to skip invalidations, and 0xF2 to skip the LLC cache. These can be combined with six implementation-specific hints – 0x26, 0x2E, 0x36, 0x3E, 0x64, and 0x65 – potentially creating instructions up to 12 bytes long. The purpose of these hints could be to target different types of stores (code, data, streaming) or to enable programmable behavior at various cache levels.
This is not the first disclosure from this unidentified entity. Previous messages on the Linux kernel mailing list, beginning last October and detailed in July, concerned x86 opcode/CPUID/MSR allocations and AMX implementations. The timing of these disclosures coincides with reports of RosaicLabs gaining access to Intel Atom processor designs, leading to speculation about their potential involvement.
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