The GNU Compiler Collection (GCC) 17, slated for release in early 2027, will now support the `-mtune=native` and `-mcpu=native` flags for RISC-V systems. This allows the compiler to optimize code generation specifically for the detected CPU, a feature previously unavailable. The update addresses a limitation requiring users to manually specify CPU types like "sifive-p550" or "spacemit-x100".
Until now, GCC lacked support for these “native” optimization flags on RISC-V, despite offering them for other architectures. The newly merged code, contributed by SiFive’s Kito Cheng, corrects this oversight. This change enables GCC to correctly interpret and utilize the `-mcpu=native` and `-mtune=native` options when compiling for RISC-V.
However, a current limitation exists for RISC-V designs employing multiple core types, such as the SpacemiT A100 and X100 combinations. In these scenarios, GCC determines the CPU type based on the core where the compiler process is running.
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